Power Factor Correction ICs

20 Jun

Most electronic systems use ac-dc switchmode power converters that draw current from the powerline in a non-sinusoidal fashion. This results in current and voltage distortions that can create problems with other equipment connected to the powerline.

Power factor describes the power relationships on an ac powerline . Current and voltage distortions occur with a reactive load, which has a real and a reactive power component. The vector sum of these two power components is the apparent power to the load. The phase angle between the real power and reactive power is the power factor angle. With a resistive load, the reactive power is zero and the apparent power equals the real power and the power factor is unity, or 100%. If the load is reactive, the power factor is lower (less than 100%).

For a nonlinear load with a distorted current waveform, the current consists of fundamental line frequency and various multiples. These harmonic currents do not contribute directly to the useful power dissipated in the load, but rather adds to the reactive power to create a higher value of apparent power. Total harmonic distortion, THD, is a common way of specifying and measuring the amount of distortion present on a waveform. Note that THD can be higher than 100%.

Most commonly used techniques for power system electronics incorporate a power factor correction (PFC) circuit ahead of the other electronics on the assembly. An example would be the PFC correction circuitry on the front-end of an off-line ac-dc power converter. In addition, most systems that employ an active PFC utilize feedback circuitry along with switchmode converters to synthesize input current waveforms consistent with high power factor.

An ac-dc power supply usually consists of a bridge rectifier followed by a input capacitor and the power stage. The capacitor reduces the ripple on the voltage waveform into the dc converter stage. The result is that large current pulses are drawn from the line over very short periods of time. This produces a spectrum of harmonic signals that may interfere with other equipment.

The impact of the added circuitry is:
Additional cost and complexity for the power converter
Lower power converter reliability
Slightly lower efficiency

Active PFC circuits are based on switchmode converter techniques and are designed to compensate for distortion as well as displacement on the input current waveform. They tend to be significantly more complex, but this complexity is becoming more manageable with the availability of specialized control ICs for implementing active PFC. Active PFC operates at frequencies higher than the line frequency so that compensation of both distortion and displacement can occur within the timeframe of each line frequency cycle, resulting in corrected power factors of up to 0.99.

The boost topology is the most popular PFC implementation. Almost all present day boost PFC converters utilize a standard controller chip for the purposes of ease of design, reduced circuit complexity and cost savings. These ICs greatly simplify the process of achieving a reliable high-performance circuit. In order for the converter to achieve power factor correction over the entire range of input line voltages, the converter in the PFC circuit must be designed so that the output voltage is greater than the peak of the input line voltage.
The active boost circuit corrects for deficiencies in both displacement and distortion. Its duty cycle is longest when the instantaneous value of the ac is near zero and shortest during peaks of each half cycle.

This PFC topology allows automatic range switching on the ac input at essentially no extra cost. Since this universal input function is now a requirement on the majority of power converters to allow for operation in all countries without any manual settings, this feature helps offset the cost of the additional componentry for the PFC function. Because the circuit operates at high frequencies, typically over 100kHz, the inductor tends to be small and light.

The efficiency of the active boost circuit is very high, approaching 95%. However, it will constitute a second conversion stage in some applications and can somewhat degrade the overall power conversion efficiency compared to a solution without PFC.

Considering all the tradeoffs, the active boost is a very good solution for many applications, especially where the power level is high enough so that the cost of the extra components is not a big percentage of the total cost.

Present standards relate to conducted harmonic emissions. When designing for an international market, therefore, a common strategy is to design to the latest European standards. The latest version, EN61000-3- 2, applies to equipment with input power between 75W and 1000W and divides equipment into four classes, only two of which will apply to power conversion applications. Power converters are either Class A or Class D, depending upon the shape of the input current waveform.

Descriptions of typical power factor correction IC are given below.
1. This space-saving controller for power factor corrected, switchmode power supplies offers low start-up and operating currents. Power Factor Correction (PFC) offers the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply fully compliant to IEC1000-3-2 specifications.

The IC includes circuits for the implementation of a leading edge, average current “boost” type PFC and a trailing edge, PWM. In one version the PFC and PWM operate at the same frequency, 67kHz. In the other version, the PFC frequency is automatically set at half that of the 134kHz PWM. This higher frequency allows the user to design with smaller PWM components while maintaining the optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load.

The PFC section also includes peak current limiting for enhanced system reliability.

Among its features are low supply currents; start-up: 150µA typ., operating: 2mA typ., overvoltage, UVLO, and brownout protection, and synchronized leading and trailing edge modulation.

2. This high performance active power factor correction is optimized for electronic ballast and low power, high density power supplies that require minimum board area reduced component count and low power dissipation. It employs an external power MOSFET.

A single quadrant, two-input multiplier is the critical element that enables this device to provide power factor correction. One input of multiplier connects to an external resistor divider that monitors the rectified ac line voltage. The other input is internally driven by a dc voltage that is the difference between the error amplifier output and reference voltage, VREF.

The multiplier has an extremely linear transfer curve over a wide dynamic range, 0V to 3.8V for Pin 3, and 2.25V to 6V for error amplifier output under all line and load conditions. The multiplier output controls the current sense comparator threshold voltage as the ac voltage traverses sinusoidally from zero to peak line. This allows the inductor peak current to follow the ac line, thus forcing the average input current to be sinusoidal. In other words, this has the effect of forcing the MOSFET on-time to track the input line voltage, resulting in a fixed drive output on-time, thus making the pre-converter load appear to be resistive to the ac line.

Internally clamping the error amplifier and multiplier outputs improves turn on overshoot characteristics and current limiting. Special protection circuitry prevents no load runaway conditions. Independent of supply voltage, the output drive clamping circuit limits overshoot of the power MOSFET gate drive, which enhances system reliability.

The IC operates as a critical conduction current mode controller. Its zero current detector turns on the external MOSFET as the voltage across the boost inductor reverses, just after the current through the boost inductor has gone to zero. The slope of the inductor current is indirectly detected by monitoring the voltage across an auxiliary winding and connecting it to the zero current detector. Once the inductor current reaches ground level, the polarity of the voltage across the winding is reversed.

A watchdog timer eliminates the need for an external oscillator when used in standalone applications. The timer provides a means to start or restart the pre-converter automatically if the drive output has been off for more than 150µs after the inductor current reached zero.

3. This IC employs a superior performance multiplier, making the device capable of working in wide input voltage range applications (from 85V to 265V) with an excellent THD. Start up current is a few tens of mA and a disable function, implemented on the ZCD pin, guarantees lower current consumption in stand by mode.

The totem pole output stage can drive a power MOSFET or IGBT with source and sink currents of ±400mA. The device is operating in transition mode and it is optimized for electronic lamp ballast application, ac-dc adaptors and switchmode power supplies. The output voltage is expected to be kept by the operation of the PFC circuit close to its nominal value. This is set by the ratio of the two external resistors R1 and R2, taking into consideration that the non inverting input of the error amplifier is biased inside the IC at 2.5V.

Current is monitored inside the IC and when it reaches about 37mA the output voltage of the multiplier is forced to decrease, reducing the power drawn from the mains. If the current exceeds 40mA, the OVP protection is triggered (Dynamic OVP), and the external power transistor switches off until the current falls approximately below10mA. However, if the overvoltage persists, an internal comparator (Static OVP) confirms the OVP condition and keeps the external power switch turned off.

The zero current detector (ZCD) can be used for device disabling as well. By grounding the ZCD voltage the device is disabled, reducing the supply current consumption at 1.4mA typical (@ 14.5V supply voltage). Releasing the ZCD pin the internal start-up timer will restart the device.

4. This active, power factor correction controller can operate over a wide range of input voltages, and output power levels in 50/60 Hz power systems. This controller offers several different protection methods to assure safe, reliable operation under any conditions. The PWM is a fixed frequency, average current mode controller with a wide complement of features. These features allow for both flexibility as well as precision in its application to a circuit. True power limiting maintains excellent power factor even in constant power mode. It also contains features that allow for fast transient response to changing load currents and line voltages.

Several features protect the device and circuit from overload and stressful conditions, including: output voltage overshoot, low line input, instantaneous current limit, line frequency current limit, and maximum power limit. Low line input protection uses the shutdown circuitry to assure that the unit does not start under low line condition. PFC converters typically are designed with an output voltage of 400Vdc. To reduce this to the level of the 4.0V reference, a 100:1 ratio is required for the voltage divider to the FB/SD pin.

An overshoot comparator monitors the output voltage. Due to the slow transient response of a PFC controller, a fast load dump can cause a large output voltage transient to occur. The overshoot comparator uses the same input as the feedback and shutdown signals. Its reference is set 8% higher than the reference used by the error amplifier. This comparator shuts down the output stage if the output voltage exceeds the set level by 8%. The circuit resumes operation once the voltage reduces to within 8% of the set level.

When energized, the converter output voltage is the peak line voltage. If the peak line voltage does not exceed 75V (0.75V at the FB/SD pin) the unit will not start. This corresponds to a line voltage of 53V rms. If desired, you can override this feature.

The output of the reference multiplier determines the current that will be required for the unit to regulate. The sum of the input voltage from the Average Current Compensation amplifier and the averaged current signal from the current sense amplifier must add to the level of the reference multiplier. The output of this multiplier is clamped to a 4.5 maximum level. The maximum average current is set by an external resistor. This form of protection is slower than the cycle-by-cycle current limiting, but faster than the maximum power limit circuit.

5. This PFC controller for low-to-medium power applications complies with IEC 1000-3-2 harmonic reduction standard. It is designed for controlling a boost pre-regulator operating in transition mode (also referred to as boundary conduction mode or critical conduction mode operation). It features a transconductance voltage amplifier for feedback error processing, a simple multiplier for generating a current command proportional to the input voltage, a current-sense (PWM) comparator, PWM logic and a totem-pole driver for driving an external MOSFET.

The PWM circuit is self-oscillating with the turn-on being governed by an inductor zero-current detector (ZCD pin) and the turn-off being governed by the current-sense comparator. Additionally, the controller provides features such as peak current limit, default timer, overvoltage protection (OVP) and enable.
System performance is enhanced by incorporation of zero power detect function, which allows the controller output to shut down at light load conditions without running into overvoltage. The device also features innovative slew rate enhancement circuits that improve the large signal transient performance of the voltage error amplifier. The low start-up and operating currents of the device results in low power consumption and ease of start-up. Highly accurate internal bandgap reference leads to tight regulation of output voltage in normal and OVP conditions, resulting in higher system reliability.

Undervoltage lockout, with its high start-up voltage and wide hysteresis, also facilitates quicker and easier start-up with a smaller VCC capacitance. The enable comparator ensures that the controller is off if the feedback sense path is broken or if the input voltage is very low.

6. This series of combination PFC/PWM controllers provide complete control functionality for any off-line power system requiring compliance with the IEC1000?3?2 harmonic reduction requirements. Combining the control and drive signals for the PFC and the PWM stages into a single device provides significant performance gains. Managing the modulation mechanisms of the two stages (leading-edge modulation for PFC and trailing-edge modulation for PWM), minimizes ripple current in the boost capacitor.

ICs are based on the average current mode control architecture with input voltage feedforward of prior PFC/PWM combination controllers. Two new key PWM features are programmable maximum duty cycle and the 2x PWM frequency options to the base PFC frequency. For the PFC stage, the devices feature an improved multiplier and the use of a transconductance amplifier for enhanced transient response.

The PWM stage features programmable maximum duty cycle and PWM frequency options that are twice the base PFC frequency. For the PFC stage, the controllers offer enhanced transient response through an improved multiplier and a transconductance amplifier.

The core of the PFC section is in a three-input multiplier that generates the reference signal for the line current. The IC series features a highly linearized multiplier circuit capable of producing a low distortion reference for the line current over the full range of line and load
conditions. A low-offset, high-bandwidth current error amplifier ensures that the actual inductor current (sensed through a resistor in the return path) follows the multiplier output command signal. The output voltage error is processed through a transconductance voltage amplifier.

The series also features high current gate drive outputs rated at 3A sink and 2A source to reduce switching losses in the power devices and to allow higher frequency operation. The family offers different undervoltage lockout (UVLO) threshold options for both PFC and PWM stages to support different bias schemes and load transient requirements.

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